Normal view MARC view ISBD view

Digital Logic Testing and Simulation (Record no. 2358)

MARC details
000 -LEADER
fixed length control field	11081nam a22001817a 4500
005 - DATE AND TIME OF LATEST TRANSACTION
control field	20240731120216.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field	240731b \|\|\|\|\|\|\|\| \|\|\|\| 00\| 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number	9780471439950
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number	621.381
Item number	MIC
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name	Miczo,Alexander
245 ## - TITLE STATEMENT
Title	Digital Logic Testing and Simulation
Statement of responsibility, etc.	Alexander Miczo
250 ## - EDITION STATEMENT
Edition statement	Edition 2
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Name of publisher, distributor, etc.	Wiley
Date of publication, distribution, etc.	2003
300 ## - PHYSICAL DESCRIPTION
Page number	673p
505 ## - FORMATTED CONTENTS NOTE
Title	1 Introduction.<br/><br/>1.1 Introduction.<br/><br/>1.2 Quality.<br/><br/>1.3 The Test.<br/><br/>1.4 The Design Process.<br/><br/>1.5 Design Automation.<br/><br/>1.6 Estimating Yield.<br/><br/>1.7 Measuring Test Effectiveness.<br/><br/>1.8 The Economics of Test.<br/><br/>1.9 Case Studies.<br/><br/>1.9.1 The Effectiveness of Fault Simulation.<br/><br/>1.9.2 Evaluating Test Decisions.<br/><br/>1.10 Summary.<br/><br/>Problems.<br/><br/>References.<br/><br/>2 Simulation.<br/><br/>2.1 Introduction.<br/><br/>2.2 Background.<br/><br/>2.3 The Simulation Hierarchy.<br/><br/>2.4 The Logic Symbols.<br/><br/>2.5 Sequential Circuit Behavior.<br/><br/>2.6 The Compiled Simulator.<br/><br/>2.6.1 Ternary Simulation.<br/><br/>2.6.2 Sequential Circuit Simulation.<br/><br/>2.6.3 Timing Considerations.<br/><br/>2.6.4 Hazards.<br/><br/>2.6.5 Hazard Detection.<br/><br/>2.7 Event-Driven Simulation.<br/><br/>2.7.1 Zero-Delay Simulation.<br/><br/>2.7.2 Unit-Delay Simulation.<br/><br/>2.7.3 Nominal-Delay Simulation.<br/><br/>2.8 Multiple-Valued Simulation.<br/><br/>2.9 Implementing the Nominal-Delay Simulator.<br/><br/>2.9.1 The Scheduler.<br/><br/>2.9.2 The Descriptor Cell.<br/><br/>2.9.3 Evaluation Techniques.<br/><br/>2.9.4 Race Detection in Nominal-Delay Simulation.<br/><br/>2.9.5 Min–Max Timing.<br/><br/>2.10 Switch-Level Simulation.<br/><br/>2.11 Binary Decision Diagrams.<br/><br/>2.11.1 Introduction.<br/><br/>2.11.2 The Reduce Operation.<br/><br/>2.11.3 The Apply Operation.<br/><br/>2.12 Cycle Simulation.<br/><br/>2.13 Timing Verification.<br/><br/>2.13.1 Path Enumeration.<br/><br/>2.13.2 Block-Oriented Analysis.<br/><br/>2.14 Summary.<br/><br/>Problems.<br/><br/>References.<br/><br/>3 Fault Simulation.<br/><br/>3.1 Introduction.<br/><br/>3.2 Approaches to Testing.<br/><br/>3.3 Analysis of a Faulted Circuit.<br/><br/>3.3.1 Analysis at the Component Level.<br/><br/>3.3.2 Gate-Level Symbols.<br/><br/>3.3.3 Analysis at the Gate Level.<br/><br/>3.4 The Stuck-At Fault Model.<br/><br/>3.4.1 The AND Gate Fault Model.<br/><br/>3.4.2 The OR Gate Fault Model.<br/><br/>3.4.3 The Inverter Fault Model.<br/><br/>3.4.4 The Tri-State Fault Model.<br/><br/>3.4.5 Fault Equivalence and Dominance.<br/><br/>3.5 The Fault Simulator: An Overview.<br/><br/>3.6 Parallel Fault Processing.<br/><br/>3.6.1 Parallel Fault Simulation.<br/><br/>3.6.2 Performance Enhancements.<br/><br/>3.6.3 Parallel Pattern Single Fault Propagation.<br/><br/>3.7 Concurrent Fault Simulation.<br/><br/>3.7.1 An Example of Concurrent Simulation.<br/><br/>3.7.2 The Concurrent Fault Simulation Algorithm.<br/><br/>3.7.3 Concurrent Fault Simulation: Further Considerations.<br/><br/>3.8 Delay Fault Simulation.<br/><br/>3.9 Differential Fault Simulation.<br/><br/>3.10 Deductive Fault Simulation.<br/><br/>3.11 Statistical Fault Analysis.<br/><br/>3.12 Fault Simulation Performance.<br/><br/>3.13 Summary.<br/><br/>Problems.<br/><br/>References.<br/><br/>4 Automatic Test Pattern Generation.<br/><br/>4.1 Introduction.<br/><br/>4.2 The Sensitized Path.<br/><br/>4.2.1 The Sensitized Path: An Example.<br/><br/>4.2.2 Analysis of the Sensitized Path Method.<br/><br/>4.3 The D-Algorithm.<br/><br/>4.3.1 The D-Algorithm: An Analysis.<br/><br/>4.3.2 The Primitive D-Cubes of Failure.<br/><br/>4.3.3 Propagation D-Cubes.<br/><br/>4.3.4 Justification and Implication.<br/><br/>4.3.5 The D-Intersection.<br/><br/>4.4 Testdetect.<br/><br/>4.5 The Subscripted D-Algorithm.<br/><br/>4.6 PODEM.<br/><br/>4.7 FAN.<br/><br/>4.8 Socrates.<br/><br/>4.9 The Critical Path.<br/><br/>4.10 Critical Path Tracing.<br/><br/>4.11 Boolean Differences.<br/><br/>4.12 Boolean Satisfiability.<br/><br/>4.13 Using BDDs for ATPG.<br/><br/>4.13.1 The BDD XOR Operation.<br/><br/>4.13.2 Faulting the BDD Graph.<br/><br/>4.14 Summary.<br/><br/>Problems.<br/><br/>References.<br/><br/>5 Sequential Logic Test.<br/><br/>5.1 Introduction.<br/><br/>5.2 Test Problems Caused by Sequential Logic.<br/><br/>5.2.1 The Effects of Memory.<br/><br/>5.2.2 Timing Considerations.<br/><br/>5.3 Sequential Test Methods.<br/><br/>5.3.1 Seshu’s Heuristics.<br/><br/>5.3.2 The Iterative Test Generator.<br/><br/>5.3.3 The 9-Value ITG.<br/><br/>5.3.4 The Critical Path.<br/><br/>5.3.5 Extended Backtrace.<br/><br/>5.3.6 Sequential Path Sensitization.<br/><br/>5.4 Sequential Logic Test Complexity.<br/><br/>5.4.1 Acyclic Sequential Circuits.<br/><br/>5.4.2 The Balanced Acyclic Circuit.<br/><br/>5.4.3 The General Sequential Circuit.<br/><br/>5.5 Experiments with Sequential Machines.<br/><br/>5.6 A Theoretical Limit on Sequential Testability.<br/><br/>5.7 Summary.<br/><br/>Problems.<br/><br/>References.<br/><br/>6 Automatic Test Equipment.<br/><br/>6.1 Introduction.<br/><br/>6.2 Basic Tester Architectures.<br/><br/>6.2.1 The Static Tester.<br/><br/>6.2.2 The Dynamic Tester.<br/><br/>6.3 The Standard Test Interface Language.<br/><br/>6.4 Using the Tester.<br/><br/>6.5 The Electron Beam Probe.<br/><br/>6.6 Manufacturing Test.<br/><br/>6.7 Developing a Board Test Strategy.<br/><br/>6.8 The In-Circuit Tester.<br/><br/>6.9 The PCB Tester.<br/><br/>6.9.1 Emulating the Tester.<br/><br/>6.9.2 The Reference Tester.<br/><br/>6.9.3 Diagnostic Tools.<br/><br/>6.10 The Test Plan.<br/><br/>6.11 Visual Inspection.<br/><br/>6.12 Test Cost.<br/><br/>6.13 Summary.<br/><br/>Problems.<br/><br/>References.<br/><br/>7 Developing a Test Strategy.<br/><br/>7.1 Introduction.<br/><br/>7.2 The Test Triad.<br/><br/>7.3 Overview of the Design and Test Process.<br/><br/>7.4 A Testbench.<br/><br/>7.4.1 The Circuit Description.<br/><br/>7.4.2 The Test Stimulus Description.<br/><br/>7.5 Fault Modeling.<br/><br/>7.5.1 Checkpoint Faults.<br/><br/>7.5.2 Delay Faults.<br/><br/>7.5.3 Redundant Faults.<br/><br/>7.5.4 Bridging Faults.<br/><br/>7.5.5 Manufacturing Faults.<br/><br/>7.6 Technology-Related Faults.<br/><br/>7.6.1 MOS.<br/><br/>7.6.2 CMOS.<br/><br/>7.6.3 Fault Coverage Results in Equivalent Circuits.<br/><br/>7.7 The Fault Simulator.<br/><br/>7.7.1 Random Patterns.<br/><br/>7.7.2 Seed Vectors.<br/><br/>7.7.3 Fault Sampling.<br/><br/>7.7.4 Fault-List Partitioning.<br/><br/>7.7.5 Distributed Fault Simulation.<br/><br/>7.7.6 Iterative Fault Simulation.<br/><br/>7.7.7 Incremental Fault Simulation.<br/><br/>7.7.8 Circuit Initialization.<br/><br/>7.7.9 Fault Coverage Profiles.<br/><br/>7.7.10 Fault Dictionaries.<br/><br/>7.7.11 Fault Dropping.<br/><br/>7.8 Behavioral Fault Modeling.<br/><br/>7.8.1 Behavioral MUX.<br/><br/>7.8.2 Algorithmic Test Development.<br/><br/>7.8.3 Behavioral Fault Simulation.<br/><br/>7.8.4 Toggle Coverage.<br/><br/>7.8.5 Code Coverage.<br/><br/>7.9 The Test Pattern Generator.<br/><br/>7.9.1 Trapped Faults.<br/><br/>7.9.2 SOFTG.<br/><br/>7.9.3 The Imply Operation.<br/><br/>7.9.4 Comprehension Versus Resolution.<br/><br/>7.9.5 Probable Detected Faults.<br/><br/>7.9.6 Test Pattern Compaction.<br/><br/>7.9.7 Test Counting.<br/><br/>7.10 Miscellaneous Considerations.<br/><br/>7.10.1 The ATPG/Fault Simulator Link.<br/><br/>7.10.2 ATPG User Controls.<br/><br/>7.10.3 Fault-List Management.<br/><br/>7.11 Summary.<br/><br/>Problems.<br/><br/>References.<br/><br/>8 Design-For-Testability.<br/><br/>8.1 Introduction.<br/><br/>8.2 Ad Hoc Design-for-Testability Rules.<br/><br/>8.2.1 Some Testability Problems.<br/><br/>8.2.2 Some Ad Hoc Solutions.<br/><br/>8.3 Controllability/Observability Analysis.<br/><br/>8.3.1 SCOAP.<br/><br/>8.3.2 Other Testability Measures.<br/><br/>8.3.3 Test Measure Effectiveness.<br/><br/>8.3.4 Using the Test Pattern Generator.<br/><br/>8.4 The Scan Path.<br/><br/>8.4.1 Overview.<br/><br/>8.4.2 Types of Scan-Flops.<br/><br/>8.4.3 Level-Sensitive Scan Design.<br/><br/>8.4.4 Scan Compliance.<br/><br/>8.4.5 Scan-Testing Circuits with Memory.<br/><br/>8.4.6 Implementing Scan Path.<br/><br/>8.5 The Partial Scan Path.<br/><br/>8.6 Scan Solutions for PCBs.<br/><br/>8.6.1 The NAND Tree.<br/><br/>8.6.2 The 1149.1 Boundary Scan.<br/><br/>8.7 Summary.<br/><br/>Problems.<br/><br/>References.<br/><br/>9 Built-In Self-Test.<br/><br/>9.1 Introduction.<br/><br/>9.2 Benefits of BIST.<br/><br/>9.3 The Basic Self-Test Paradigm.<br/><br/>9.3.1 A Mathematical Basis for Self-Test.<br/><br/>9.3.2 Implementing the LFSR.<br/><br/>9.3.3 The Multiple Input Signature Register (MISR).<br/><br/>9.3.4 The BILBO.<br/><br/>9.4 Random Pattern Effectiveness.<br/><br/>9.4.1 Determining Coverage.<br/><br/>9.4.2 Circuit Partitioning.<br/><br/>9.4.3 Weighted Random Patterns.<br/><br/>9.4.4 Aliasing.<br/><br/>9.4.5 Some BIST Results.<br/><br/>9.5 Self-Test Applications.<br/><br/>9.5.1 Microprocessor-Based Signature Analysis.<br/><br/>9.5.2 Self-Test Using MISR/Parallel SRSG (STUMPS).<br/><br/>9.5.3 STUMPS in the ES/9000 System.<br/><br/>9.5.4 STUMPS in the S/390 Microprocessor.<br/><br/>9.5.5 The Macrolan Chip.<br/><br/>9.5.6 Partial BIST.<br/><br/>9.6 Remote Test.<br/><br/>9.6.1 The Test Controller.<br/><br/>9.6.2 The Desktop Management Interface.<br/><br/>9.7 Black-Box Testing.<br/><br/>9.7.1 The Ordering Relation.<br/><br/>9.7.2 The Microprocessor Matrix.<br/><br/>9.7.3 Graph Methods.<br/><br/>9.8 Fault Tolerance.<br/><br/>9.8.1 Performance Monitoring.<br/><br/>9.8.2 Self-Checking Circuits.<br/><br/>9.8.3 Burst Error Correction.<br/><br/>9.8.4 Triple Modular Redundancy.<br/><br/>9.8.5 Software Implemented Fault Tolerance.<br/><br/>9.9 Summary.<br/><br/>Problems.<br/><br/>References.<br/><br/>10 Memory Test.<br/><br/>10.1 Introduction.<br/><br/>10.2 Semiconductor Memory Organization.<br/><br/>10.3 Memory Test Patterns.<br/><br/>10.4 Memory Faults.<br/><br/>10.5 Memory Self-Test.<br/><br/>10.5.1 A GALPAT Implementation.<br/><br/>10.5.2 The 9N and 13N Algorithms.<br/><br/>10.5.3 Self-Test for BIST.<br/><br/>10.5.4 Parallel Test for Memories.<br/><br/>10.5.5 Weak Read–Write.<br/><br/>10.6 Repairable Memories.<br/><br/>10.7 Error Correcting Codes.<br/><br/>10.7.1 Vector Spaces.<br/><br/>10.7.2 The Hamming Codes.<br/><br/>10.7.3 ECC Implementation.<br/><br/>10.7.4 Reliability Improvements.<br/><br/>10.7.5 Iterated Codes.<br/><br/>10.8 Summary.<br/><br/>Problems.<br/><br/>References.<br/><br/>11 IDDQ.<br/><br/>11.1 Introduction.<br/><br/>11.2 Background.<br/><br/>11.3 Selecting Vectors.<br/><br/>11.3.1 Toggle Count.<br/><br/>11.3.2 The Quietest Method.<br/><br/>11.4 Choosing a Threshold.<br/><br/>11.5 Measuring Current.<br/><br/>11.6 IDDQ Versus Burn-In.<br/><br/>1.7 Problems with Large Circuits.<br/><br/>11.8 Summary.<br/><br/>Problems.<br/><br/>References.<br/><br/>12 Behavioral Test and Verification.<br/><br/>12.1 Introduction.<br/><br/>12.2 Design Verification: An Overview.<br/><br/>12.3 Simulation.<br/><br/>12.3.1 Performance Enhancements.<br/><br/>12.3.2 HDL Extensions and C++.<br/><br/>12.3.3 Co-design and Co-verification.<br/><br/>12.4 Measuring Simulation Thoroughness.<br/><br/>12.4.1 Coverage Evaluation.<br/><br/>12.4.2 Design Error Modeling.<br/><br/>12.5 Random Stimulus Generation.<br/><br/>12.6 The Behavioral ATPG.<br/><br/>12.6.1 Overview.<br/><br/>12.6.2 The RTL Circuit Image.<br/><br/>12.6.3 The Library of Parameterized Modules.<br/><br/>12.6.4 Some Basic Behavioral Processing Algorithms.<br/><br/>12.7 The Sequential Circuit Test Search System (SCIRTSS).<br/><br/>12.7.1 A State Traversal Problem.<br/><br/>12.7.2 The Petri Net.<br/><br/>12.8 The Test Design Expert.<br/><br/>12.8.1 An Overview of TDX.<br/><br/>12.8.2 DEPOT.<br/><br/>12.8.3 The Fault Simulator.<br/><br/>12.8.4 Building Goal Trees.<br/><br/>12.8.5 Sequential Conflicts in Goal Trees.<br/><br/>12.8.6 Goal Processing for a Microprocessor.<br/><br/>12.8.7 Bidirectional Goal Search.<br/><br/>12.8.8 Constraint Propagation.<br/><br/>12.8.9 Pitfalls When Building Goal Trees.<br/><br/>12.8.10 MaxGoal Versus MinGoal.<br/><br/>12.8.11 Functional Walk.<br/><br/>12.8.12 Learn Mode.<br/><br/>12.8.13 DFT in TDX.<br/><br/>12.9 Design Verification.<br/><br/>12.9.1 Formal Verification.<br/><br/>12.9.2 Theorem Proving.<br/><br/>12.9.3 Equivalence Checking.<br/><br/>12.9.4 Model Checking.<br/><br/>12.9.5 Symbolic Simulation.<br/><br/>12.10Summary.<br/><br/>Problems.<br/><br/>References.<br/><br/>Index.<br/><br/>
520 ## - SUMMARY, ETC.
Summary, etc.	Your road map for meeting today's digital testing challengesToday, digital logic devices are common in products that impact public safety, including applications in transportation and human implants. Accurate testing has become more critical to reliability, safety, and the bottom line. Yet, as digital systems become more ubiquitous and complex, the challenge of testing them has become more difficult. As one development group designing a RISC stated, ""the work required to . . . test a chip of this size approached the amount of effort required to design it.
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme	Dewey Decimal Classification
Koha item type	Books
952 ## - LOCATION AND ITEM INFORMATION (KOHA)
--	7049

Holdings
Withdrawn status	Lost status	Source of classification or shelving scheme	Damaged status	Not for loan	Collection code	Home library	Current library	Shelving location	Date acquired	Source of acquisition	Cost, normal purchase price	Inventory number	Total Checkouts	Full call number	Barcode	Date last seen	Cost, replacement price	Price effective from	Currency	Koha item type
		Dewey Decimal Classification			Non-fiction	IIITDM Kurnool	IIITDM Kurnool	ELECTRONICS COMMUNICATION ENGINEERING	31.07.2024	Narendra Publishing House	225.95	NPH/24-25/IN-00122 DT 22/7/2024		621.381 MIC	0006054	31.07.2024	225.95	31.07.2024	USD	Books