MARC details
| 000 -LEADER |
|---|
| fixed length control field |
01423nam a22002177a 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20200916164425.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
190107b ||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9789332584464 |
| 040 ## - CATALOGING SOURCE |
|---|
| Transcribing agency |
0 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.304 |
| Item number |
CIL |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Ciletti Michael |
| 245 ## - TITLE STATEMENT |
|---|
| Title |
Advanced digital design with the verilog HDL |
| Statement of responsibility, etc. |
Michael D. Ciletti. |
| 250 ## - EDITION STATEMENT |
|---|
| Edition statement |
2/e |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Boston : |
| Name of publisher, distributor, etc. |
Prentice Hall, |
| Date of publication, distribution, etc. |
©2011. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Page number |
xviii, 965 pages : |
| Other physical details |
illustrations ; |
| Dimensions |
24 cm |
| 505 ## - FORMATTED CONTENTS NOTE |
|---|
| Title |
Introduction to digital design methodology --<br/>. |
| -- |
Review of combinational logic design --<br/> |
| -- |
Fundamentals of sequential logic design --<br/> |
| -- |
Introduction to logic design with Verilog --<br/> |
| -- |
Logic design with behavioral models of combinational and sequential logic --<br/> |
| -- |
Synthesis of combinational and sequential logic --<br/> |
| -- |
Design and synthesis of datapath controllers --<br/> |
| -- |
Programmable logic and storage devices --<br/> |
| -- |
Algorithms and architectures for digital processors --<br/> |
| -- |
Architectures for arithmetic processors --<br/> |
| -- |
Postsynthesis design tasks |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
<br/>Aimed at advanced courses in digital design for seniors and first-year graduate students in electrical engineering, computer engineering, and computer science, this book assumes and builds on the background of a first course in logic design |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Logic design -- Data processing. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Verilog (Computer hardware description language) |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Books |
| 952 ## - LOCATION AND ITEM INFORMATION (KOHA) |
|---|
| -- |
1223 |
| 952 ## - LOCATION AND ITEM INFORMATION (KOHA) |
|---|
| -- |
1224 |
| 952 ## - LOCATION AND ITEM INFORMATION (KOHA) |
|---|
| -- |
1225 |
| 952 ## - LOCATION AND ITEM INFORMATION (KOHA) |
|---|
| -- |
1567 |
| 952 ## - LOCATION AND ITEM INFORMATION (KOHA) |
|---|
| -- |
1568 |
| 952 ## - LOCATION AND ITEM INFORMATION (KOHA) |
|---|
| -- |
1569 |
| 952 ## - LOCATION AND ITEM INFORMATION (KOHA) |
|---|
| -- |
1570 |
| 952 ## - LOCATION AND ITEM INFORMATION (KOHA) |
|---|
| -- |
1571 |
| 952 ## - LOCATION AND ITEM INFORMATION (KOHA) |
|---|
| -- |
1572 |
| 952 ## - LOCATION AND ITEM INFORMATION (KOHA) |
|---|
| -- |
1573 |
