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Digital design: with an introduction to the verilog HDL M. Morris Mano, Michael D. Ciletti.
Material type:
TextPublication details: Pearson 2016 ChennaiEdition: 5/eDescription: xv, 547 pages : illustrations ; 25 cmISBN: - 9788131794746
- 621.304 MAN
Contents:
1. Digital Systems and Binary Numbers -- 2. Boolean Algebra and Logic Gates -- 3. Gate-Level Minimization -- 4. Combinational Logic -- 5. Synchronous Sequential Logic -- 6. Registers and Counters -- 7. Memory and Programmable Logic -- 8. Design at the Register Transfer Level -- 9. Laboratory Experiments with Standard ICs and FPGAs 10. Standard Graphic Symbols --
| Item type | Current library | Call number | Status | Notes | Date due | Barcode |
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IIITDM Kurnool General Stacks | 621.3.049.77 MAN (Browse shelf(Opens below)) | Available | ECE | 0000552 | |
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Books
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IIITDM Kurnool General Stacks | 621.3.049.77 MAN (Browse shelf(Opens below)) | Available | ECE | 0000553 | |
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Books
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IIITDM Kurnool General Stacks | 621.3.049.77 MAN (Browse shelf(Opens below)) | Available | ECE | 0000554 |
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| 621.3.049.77 LEA Digital Principles and Applications | 621.3.049.77 LEA Digital Principles and Applications | 621.3.049.77 MAN Digital design: with an introduction to the verilog HDL | 621.3.049.77 MAN Digital design: with an introduction to the verilog HDL | 621.3.049.77 MAN Digital design: with an introduction to the verilog HDL | 621.3.049.77 MAN Digital Design: With an Introduction to the Verilog HDL, VHDL and System Verilog | 621.3.049.77 MAN Digital Design: With an Introduction to the Verilog HDL, VHDL and System Verilog |
1. Digital Systems and Binary Numbers -- 2. Boolean Algebra and Logic Gates -- 3. Gate-Level Minimization -- 4. Combinational Logic -- 5. Synchronous Sequential Logic -- 6. Registers and Counters -- 7. Memory and Programmable Logic -- 8. Design at the Register Transfer Level -- 9. Laboratory Experiments with Standard ICs and FPGAs 10. Standard Graphic Symbols --
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