Image from Amazon.com
Computer Architecture and Organisation
Material type:
TextPublication details: Chennai : McGraw Hill Education Indian, 2002.Edition: 2nd EditionDescription: various pagination : ill.; 24 cmISBN: - 9780070141797
- 004.2
Contents:
Computer Organisation Computer Arithmetic Instruction sets and the Processor Organisations Basic Processing Unit - Register Transfer Language, Microoperations, Hardwired and Microprogrammed Contral Unit Organisation Instruction Pipelining and Parallel Processing Instruction - Level Parallelism - VLIW, Vector, Array and Multithreaded Processors and using Parallel Optimizing Compiler The Memory System Caches Virtual Memory Input/Output Organisation Multiprocessor Architectures
| Item type | Current library | Collection | Call number | Status | Date due | Barcode |
|---|---|---|---|---|---|---|
Books
|
IIITDM Kurnool General Stacks | 004.2 CAR (Browse shelf(Opens below)) | Available | 0001542 | ||
Reference
|
IIITDM Kurnool Reference | Reference | 004.2 CAR (Browse shelf(Opens below)) | Not For Loan | 0001543 | |
|
Books
|
IIITDM Kurnool General Stacks | 004.2 CAR (Browse shelf(Opens below)) | Available | 0001544 | ||
|
Books
|
IIITDM Kurnool General Stacks | 004.2 CAR (Browse shelf(Opens below)) | Available | 0001545 | ||
|
Books
|
IIITDM Kurnool General Stacks | 004.2 CAR (Browse shelf(Opens below)) | Available | 0001546 |
Browsing IIITDM Kurnool shelves, Shelving location: Reference, Collection: Reference Close shelf browser (Hides shelf browser)
|
|
|
|
|
|
|
||
| 004.056 STA Cryptography and network security:principles and practice | 004.1 NIE Quantum computation and quantum information | 004.16 SIE Real-Time Embedded Components and Systems with Linux and RTOS | 004.2 CAR Computer Architecture and Organisation | 004.2 MAN Computer system architecture | 004.22 HEN Computer architecture : | 004.231 FUR ARM system-on-chip architecture |
Computer Organisation Computer Arithmetic Instruction sets and the Processor Organisations Basic Processing Unit - Register Transfer Language, Microoperations, Hardwired and Microprogrammed Contral Unit Organisation Instruction Pipelining and Parallel Processing Instruction - Level Parallelism - VLIW, Vector, Array and Multithreaded Processors and using Parallel Optimizing Compiler The Memory System Caches Virtual Memory Input/Output Organisation Multiprocessor Architectures
There are no comments on this title.