Formal verification : an essential toolkit for modern VLSI design / Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar.
Material type:
TextPublisher: Amsterdam ; Boston : Elsevier/MK, Morgan Kaufmann is an imprint of Elsevier, [2015]Copyright date: ©2015Description: xvii, 353 pages : illustrations ; 24 cmContent type: - text
- unmediated
- volume
- 9780128007273
- 0128007273
- Essential toolkit for modern VLSI design
- Essential toolkit for modern very large-scale integration design
- Electronic circuits
- Integrated circuits
- Verilog (Computer hardware description language)
- Electronic circuits
- Integrated circuits
- Verilog (Computer hardware description language)
- -- Testing
- -- Very large scale integration -- Design and construction
- -- Testing
- -- Very large scale integration -- Design and construction
- 621.3 SEL 23
| Item type | Current library | Call number | Status | Date due | Barcode |
|---|---|---|---|---|---|
Books
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IIITDM Kurnool General Stacks | 621.3 SEL (Browse shelf(Opens below)) | Checked out | 10.02.2025 | 0001848 |
Formal Verification: From Dreams to Reality Basic Formal Verification Algorithms Introduction to SystemVerilog Assertions Formal Property Verification Effective FPV For Design Exercise Effective FPV for Verification FPV "Apps" for Specific SOC Problems Formal Equivalence Verification Formal Verification's Greatest Bloopers: The Danger of False Positives Dealing with Complexity Your New FV-Aware Lifestyle
'Formal Verification' presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies.
Includes bibliographical references and index.
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